In the fabrication process of electronic devices, for instance, integrated circuits (ICs), it is essential to detect defects effectively at an early stage in order to maintain and improve yield rates. As IC feature sizes shrink, subtle defects may become “killer defects” which can result in improper electrical device functions. Hence, high sensitivity recipes need to be developed to capture low-signal but yield limiting defects.
One of the issues for optimizing a defect detection recipe is the existence of a large amount of nuisance defects which affects the efficiency of distinguishing the “killer defects”. For example, as the design rule gets more stringent, the main contributors of noise are not only the noise from the patterns, but also those from nuisance defects like hillocks, silicon cones and discolorations which can be significantly larger than the subtle killer defects. In order to suppress nuisance defects and locate killer defects, tremendous efforts and time need to be invested which can affect productivity.
Therefore, challenges for developing a cost-effective defect detection technique exist.